JPH0457924U - - Google Patents
Info
- Publication number
- JPH0457924U JPH0457924U JP10033790U JP10033790U JPH0457924U JP H0457924 U JPH0457924 U JP H0457924U JP 10033790 U JP10033790 U JP 10033790U JP 10033790 U JP10033790 U JP 10033790U JP H0457924 U JPH0457924 U JP H0457924U
- Authority
- JP
- Japan
- Prior art keywords
- input control
- control clock
- output terminal
- channel transistor
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Logic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10033790U JPH0457924U (en]) | 1990-09-25 | 1990-09-25 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10033790U JPH0457924U (en]) | 1990-09-25 | 1990-09-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0457924U true JPH0457924U (en]) | 1992-05-19 |
Family
ID=31842911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10033790U Pending JPH0457924U (en]) | 1990-09-25 | 1990-09-25 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0457924U (en]) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6083419A (ja) * | 1983-10-13 | 1985-05-11 | Nec Corp | 出力バツフア回路 |
JPH02230818A (ja) * | 1988-11-25 | 1990-09-13 | Mitsubishi Electric Corp | 半導体装置のための出力回路 |
-
1990
- 1990-09-25 JP JP10033790U patent/JPH0457924U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6083419A (ja) * | 1983-10-13 | 1985-05-11 | Nec Corp | 出力バツフア回路 |
JPH02230818A (ja) * | 1988-11-25 | 1990-09-13 | Mitsubishi Electric Corp | 半導体装置のための出力回路 |
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